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[WIP] Switching from Synlig to Yosys-Slang #3181

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[WIP] Switching from Synlig to Yosys-Slang #3181

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loglav03
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@loglav03 loglav03 commented Jul 3, 2025 •
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Description

Replaced Synlig with the Yosys-Slang plugin for Yosys for reading SystemVerilog.

Related Issue

  1. System Verilog support is broken due to compilation error in F4PGA plugin #2821
  2. Embed slang-yosys plugin as a SystemVerilog frontend for yosys #3108

Motivation and Context

Synlig has a lot of overhead when building with the vtr build system leading to issues when building in CI and sometimes locally. Synlig is also poorly maintained. Yosys-Slang has significantly less overhead, can easily be implemented as a plugin for yosys, and is regularly maintained.

How Has This Been Tested?

Has been tested with the vtr_reg_system_verilog tests [PASSED]

Types of changes

  • [ x] Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • [ x] My change requires a change to the documentation
  • [ x] I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

loglav03 and others added 5 commits June 26, 2025 17:38
@loglav03
Added in yosys-slang as a submodule and configured it to build and in…
4f8abac 
…stall with vtr when enabled with the cmake parameter -DSLANG_SYSTEMVERILOG=ON
@loglav03
Set up yosys-slang to be used as a frontend for Yosys
efb1d87
@loglav03
Fully implemented yosys-slang as a plugin for yosys
90e180b
@loglav03
Updating configs for vtr_reg_system_verilog tests. They now read in m…
c1c2a5d 
…ultiple .sv files instead of single flattened .sv files (with the exception of the f4pga_pulse_width_led test since it uses .v files instead of .sv)
@loglav03
Merge branch 'master' into synlig_to_yosys_slang
7c4c868
@github-actions github-actions bot added lang-cpp C/C++ code build Build system lang-python Python code lang-make CMake/Make code external_libs labels Jul 3, 2025
@github-actions github-actions bot added the infra Project Infrastructure label Jul 3, 2025
@github-actions github-actions bot added the docs Documentation label Jul 7, 2025
@loglav03
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loglav03 commented Jul 8, 2025

@petergrossmann21 - I ran tests with yosys-slang enabled on the benchmarks you listed in this PR #2885. Some of these benchmarks made it through the entire flow and passed while others failed at read_slang in Yosys or failed at the VPR stage. There are also many other benchmarks not in the list that also failed with yosys-slang. Whenever you're available Peter I'll need help with HDL file cleanup for this.

Passing VPR Benchmarks:

blob_merge
diffeq1
diffeq2
single_ff
single_wire

Failing VPR Benchmarks:

and_latch
arm_core
boundtop
ch_intrinisics
multiclock_output_and_latch
multiclock_reader_writer
multiclock_separate_and_latch
stereovision3

I have not tried koios yet since the benchmarks take a long time to run, but I'm sure I will see similar results.

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